The performance of memory-intensive applications is often limited by how fast the memory system can provide needed data. Latency between processors and memory is often the performance bottleneck in application performance. Multiple processor cores require highly efficient cache operation with wide memory bandwidth.
In today's world, digital system performance and complexity are continually increasing due to technology scaling and three-dimensional (3D) integration. Current designs stick to conventional cache approaches. On-demand, on-chip memory support is critical to make the most of these developments. As the gap widens between processor speed and memory access time, the need to overhaul cache architecture to keep up with digital system development trends becomes apparent.